The invention relates to a single chip microcomputer, and more particularly to a single chip microcomputer having an improved parallel transmission feature and thus an improved parallel input-output port.
A great number of single chip microcomputers are widely used in the field of computers due to a low cost, a high reliability and a low power consumption. In the general single chip microcomputers, a single chip has an integration of a processing unit, storage devices and input-output units as well as interfaces and the like. In various single chip microcomputers, well known in the art is a single chip microcomputer utilizing a parallel data transmission which implements a simultaneous transmission of a plurality of bits making up a character through a plurality of separated transmission lines. Such the parallel data transmission is applicable to input and/or output ports for access to external devices. A typical one of the single chip microcomputers including a parallel input-output port will be described with reference to FIGS. 1, 2 and 3.
In FIG. 1, the single chip microcomputer 501 includes a clock oscillation circuit 502, a processing unit 503, an interrupt control unit 504, a parallel input-output port 506, a timer circuit 508, a read only memory (a ROM) 510, a random access memory (RAM) 512 and an external bus interface 514 as well as an address bus 516 and a data bus 517. The single chip microcomputer 501 is supplied with a power from a power supply 519 for its driving and is coupled to a ground 520. The clock oscillatory circuit 502 is coupled with a quartz oscillator 518, which generates clock signals used for the synchronous data processing, so as to receive clock signals from the quartz oscillator 518 and then supply the clock signal to the central processing unit for its synchronous data processing.
The processing unit 503 for executing data processing includes circuits which control the interruption of instructions and their executions. The processing unit 521 is coupled to the interrupt control unit 504 for interruption of instructions and their executions. The processing unit 503 is coupled to an address output line 527 which connects with the address bus 516 for delivering informations of address to the address bus 516. The processing unit 503 is also coupled to a control signal input-output line 528 which connects with the address bus 516. The processing unit 503 is also coupled to a data input-output line 529 which connects with the data bus 517. The processing unit 503 is thus accessible to the random access memory 512 and the read only memory 510 through the address bus 516 and the data bus 517.
The interrupt control unit 504 has a plurality of external interrupt input terminals 521 for receipt of an interrupt request signal generated in external devices such as external memory devices. The interrupt control unit 504 is coupled to the address bus 516 through a decoder 505 for receipt of decoded signals. The interrupt control unit 504 is also coupled to the address bus 516 through an address input line 530 for obtaining address information which specifies a storage device is requesting the interruption. The interrupt control unit 504 is also coupled to the data bus 517 through a data input-output line 531.
The parallel input-output port 506 has a plurality of sets of parallel input-output terminals 522 through which the parallel data transmission to external devices is implemented. The parallel input-output port 506 is coupled to the address bus 516 through a decoder 507 for receipt of decoded signals. The parallel input-output port 506 is also coupled to the address bus 516 through an address input line 532. The parallel input-output port 506 is also coupled to the data bus 517 through a data input-output line 533.
The timer circuit 508 is coupled to timer control signal input-output lines 523 for defining a specific time duration and also coupled to the address bus 516 through a decoder 509. The timer circuit 508 is coupled to the address bus 516 through an address input line 543 and further coupled to the data bus 517 through a data input-output line 535.
The read only memory (ROM) 510 is to store instructions to be executed by the processing unit 503. The read only memory 510 is coupled to the address bus 516 through a decoder 511 and also coupled to the address bus 516 through an address input line 536. The read only memory 510 is coupled to the data bus 517 through a data output line 537.
The random access memory (RAM) 512 is to store work data to be used for data processing by the processing unit 503. The random access memory 512 is coupled to the address bus 516 through a decoder 513 and also coupled to the address bus 516 through an address input line 538. The random access memory 512 is coupled to the data bus 517 through a data input-output line 539.
The external bus interface 514 has a plurality of control input-output terminals 524, an external address bus 525 and an external data bus 526. The external bus interface 514 is coupled to the address bus 516 through a decoder 515 and also coupled to the address bus 516 through an address output line 540. The external bus interface 514 is further coupled to the data bus 517 through a data input-output line 541.
The parallel input-output port 506 will subsequently be described much more closely to explain problems with the parallel input-output port 506 in the parallel transmission. The parallel input-output port 506 comprises an integration of parallel input-output signal transmission lines, each of which transmits binary digit signals or a 0 signal and a 1 signal. It seems general that when a set of eight bits makes up data such as a character, the switching between the input and output may be conducted per eight bits. But, it may be possible to conduct the switching between the input and output per one bit, by a software stored in a register.
The parallel input-output port 506 comprises a register being able to retain binary signals. The processing unit 503 conducts the read-out or the write of the binary signals from or into the port 506. The parallel input-output port 506 at the input state allows the processing unit 503 to execute the read-out the binary state or "0"/"1" of the port 506. The parallel input-output port 506 at the output state permits the processing unit 503 to execute the write of the 8 bit data into the resister of the port 506.
In such the input-output ports, there is an input-output port for 24 bits in which a shift of the input and the output is conducted per 8 bits. The set of the input and output is conducted by setting a mode register.
The parallel input-output port physically comprises a private input port, a private output port and an input-output switchable port. The installation of the parallel input-output port in the single chip microcomputer requires a great number of private terminals. The number of pins allocated for the parallel input-output port is restricted by the total number of pins of the package which seals integrated circuits. Physically, it is necessary to have the pins allocated not only for the parallel input-output port but also for other units. For example, the parallel port and address terminals are so multiplexed as to reduce the number of pins. If the interface buses such as address bus or the data bus are used, it is impossible to use the parallel input-output port.
The size of the package and the number of pins are important factors of determining the cost of the integrated circuit. In view of the cost, it is of course desirable to reduce the number of pins of the package. On the other hand, the installation of the parallel input-output port in the single chip microcomputer, however, requires a great number of pins. In the prior art, it is therefore difficult to install the parallel input-output port in the single chip microcomputer.
Alternatively, there is a clock synchronous serial interface which is installed in the single chip microcomputer. The clock synchronous serial interface will be described with reference to FIGS. 2 and 3. The clock synchronous serial interface exhibits an analogous performance to that of the parallel input-output port. The clock synchronous serial interface includes a serial clock control circuit 614, a shift register 609 and a D-type flip-flop circuit 616. The shift register 609 is coupled to a data bus 610 which transmits 8 bit signals. The shift register 609 is also coupled to a serial data input signal line 601 through an input buffer 605 for receipt of a serial data input signal. The shift register 609 is further coupled to the D-type flip-flop circuit 616 at its input D-terminal. The serial clock control circuit 614 is coupled to a control input signal bus 615 for receipt of control signals such as a start signal. The serial clock control circuit 614 is coupled to an interrupt transfer complete output signal line 604 through an output buffer 608 for output of an interrupt transfer complete output signal INTSCI. The serial clock control circuit 614 is also coupled to the shift register 609 through a read enable signal line 613 for delivering a read enable signal RD to the shift register 609. The serial clock control circuit 614 is also coupled to the shift register 609 through a write enable signal line 612 for delivering a write enable signal WE to the shift register 609. The serial clock control circuit 614 is also coupled to the shift register 609 through a serial control clock signal line 611 for delivering a serial control clock signal SCLK to the shift register 609. The serial control clock signal line 611 is coupled to a serial synchronous clock signal output line 602 through an output buffer 606. The serial control clock signal line 611 is also coupled to the D-type flip-flop circuit 616 at its input terminal. The D-type flip-flop 616 is coupled at its output side to a serial data output signal line 603 on which an output buffer 607 is arranged.
The clock synchronous serial interface performs as a communication unit. Values or binary digit signals are transmitted through the data bus 610 to the shift register 609. The shift register 609 receives a value and then stores the same. Namely, the value comprising the binary digit is written into the shift register 609. Concurrently, the serial clock control circuit 614 generates the write enable signal WE for transmission thereof to the shift register 609 through the write enable signal line 612 thereby the serial clock control circuit 614 generates a serial control clock signal SCLK which will be delivered to the shift register 609 though the serial control clock signal line 611. The shift register 609 receives the serial control clock signal and then exhibits a serial shift of data. The serial data output signal SO is subsequently transmitted on the serial data output signal line 603 through the D-type flip-flop circuit 616 and the output buffer 607. Concurrently, the shift register 609 receives a serial data input signal SI being transmitted on the serial data input signal line 601 through the input buffer 605. That is how the serial shift of data is performed by the shift register 609. When the data transfer by the shift register 609 is completed, the serial clock control circuit 614 generates the interrupt transfer complete signal INTSCI and thus delivers the same on the interrupt transfer complete signal line 604 through the output buffer 608. When the transmission of all data is completed, the generation of the serial control clock SCLK by the serial clock control circuit 614 is completed. The wave-forms of the above signals and thus the serial control output clock signal CSLK 611, the serial data input signal SI, the serial data output signal SO and the interrupt transfer complete output signal INTCS are illustrated in FIG. 3. The clock synchronous serial interface is usable as an output port but an input port when the interrupt transfer complete output signal INTSCI serves as ENABLE signals for latch circuit. Namely, the serial clock synchronous interface is unable to serve as an input port. Further, the clock synchronous interface is engaged with a possibility of erasure of data from the shift register. It is therefore impossible to use the clock synchronous serial interface as the parallel input-output port.